/*
 * NVHOST Minimal PowerManagement Header
 *
 * Copyright (c) 2017, NVIDIA Corporation.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __NVHOST_MINIMAL_PM_H__
#define __NVHOST_MINIMAL_PM_H__

#define CLK_RST_CONTROLLER		0x20000000
#define HOST1X_THOST			0x13e00000

#define CLK_OUT_ENB_HOST1X_SET_0	(CLK_RST_CONTROLLER + 0x001e1004)
#define RST_DEV_HOST1X_CLR_0		(CLK_RST_CONTROLLER + 0x001e0008)
#define RST_DEV_CV_HOST1X_CLR_0		(CLK_RST_CONTROLLER + 0x01190014)
#define COMMON_CV_CLUSTER_CLAMP_0	(HOST1X_THOST + 0xc000)
#define COMMON_MOD_CLAMP_E_CLR_0	(HOST1X_THOST + 0xc00c)

#define RST_DEV_PVA0_CLR_0		(CLK_RST_CONTROLLER + 0x0115006c)
#define RST_DEV_PVA1_CLR_0		(CLK_RST_CONTROLLER + 0x0116006c)
#define RST_DEV_PVA0_CPU_AXI_CLR_0	(CLK_RST_CONTROLLER + 0x011500a8)
#define RST_DEV_PVA1_CPU_AXI_CLR_0	(CLK_RST_CONTROLLER + 0x011600a8)
#define RST_DEV_PVA0_DMA0_CLR_0		(CLK_RST_CONTROLLER + 0x01150078)
#define RST_DEV_PVA1_DMA0_CLR_0		(CLK_RST_CONTROLLER + 0x01160078)
#define RST_DEV_PVA0_DMA1_CLR_0		(CLK_RST_CONTROLLER + 0x01150084)
#define RST_DEV_PVA1_DMA1_CLR_0		(CLK_RST_CONTROLLER + 0x01160084)
#define RST_DEV_PVA0_PROCCFG_CLR_0	(CLK_RST_CONTROLLER + 0x01150090)
#define RST_DEV_PVA1_PROCCFG_CLR_0	(CLK_RST_CONTROLLER + 0x01160090)
#define RST_DEV_PVA0_PM_CLR_0		(CLK_RST_CONTROLLER + 0x0115009c)
#define RST_DEV_PVA1_PM_CLR_0		(CLK_RST_CONTROLLER + 0x0116009c)
#define RST_DEV_PVA0_VPS0_CLR_0		(CLK_RST_CONTROLLER + 0x011500f0)
#define RST_DEV_PVA1_VPS0_CLR_0		(CLK_RST_CONTROLLER + 0x011600f0)
#define RST_DEV_PVA0_VPS1_CLR_0		(CLK_RST_CONTROLLER + 0x011500fc)
#define RST_DEV_PVA1_VPS1_CLR_0		(CLK_RST_CONTROLLER + 0x011600fc)
#define RST_DEV_PVA0_CFG_CLR_0		(CLK_RST_CONTROLLER + 0x01150108)
#define RST_DEV_PVA1_CFG_CLR_0		(CLK_RST_CONTROLLER + 0x01160108)
#define RST_DEV_PVA0_H1X_CLR_0		(CLK_RST_CONTROLLER + 0x01150114)
#define RST_DEV_PVA1_H1X_CLR_0		(CLK_RST_CONTROLLER + 0x01160114)
#define RST_DEV_PVA0_SEC_CLR_0		(CLK_RST_CONTROLLER + 0x01150120)
#define RST_DEV_PVA1_SEC_CLR_0		(CLK_RST_CONTROLLER + 0x01160120)
#define RST_DEV_PVA0_RAM1C_CLR_0	(CLK_RST_CONTROLLER + 0x0115012c)
#define RST_DEV_PVA1_RAM1C_CLR_0	(CLK_RST_CONTROLLER + 0x0116012c)
#define RST_DEV_PVA0_ACTMON_CLR_0	(CLK_RST_CONTROLLER + 0x01150138)
#define RST_DEV_PVA1_ACTMON_CLR_0	(CLK_RST_CONTROLLER + 0x01160138)
#define RST_DEV_PVA0_TKE_CLR_0		(CLK_RST_CONTROLLER + 0x01150144)
#define RST_DEV_PVA1_TKE_CLR_0		(CLK_RST_CONTROLLER + 0x01160144)
#define RST_DEV_PVA0_TSCTN_CLR_0	(CLK_RST_CONTROLLER + 0x01150150)
#define RST_DEV_PVA1_TSCTN_CLR_0	(CLK_RST_CONTROLLER + 0x01160150)
#define RST_DEV_PVA0_GTE_CLR_0		(CLK_RST_CONTROLLER + 0x0115015c)
#define RST_DEV_PVA1_GTE_CLR_0		(CLK_RST_CONTROLLER + 0x0116015c)

#define CLK_OUT_ENB_PVA0_CPU_AXI_SET_0	(CLK_RST_CONTROLLER + 0x01150008)
#define CLK_OUT_ENB_PVA1_CPU_AXI_SET_0	(CLK_RST_CONTROLLER + 0x01160008)
#define CLK_OUT_ENB_PVA0_VPS_SET_0	(CLK_RST_CONTROLLER + 0x011500b4)
#define CLK_OUT_ENB_PVA1_VPS_SET_0	(CLK_RST_CONTROLLER + 0x011600b4)
#define CLK_OUT_ENB_PVA0_VPS0_SET_0	(CLK_RST_CONTROLLER + 0x011500c0)
#define CLK_OUT_ENB_PVA1_VPS0_SET_0	(CLK_RST_CONTROLLER + 0x011600c0)
#define CLK_OUT_ENB_PVA0_VPS1_SET_0	(CLK_RST_CONTROLLER + 0x011500cc)
#define CLK_OUT_ENB_PVA1_VPS1_SET_0	(CLK_RST_CONTROLLER + 0x011600cc)
#define CLK_OUT_ENB_PVA0_CPU_SET_0	(CLK_RST_CONTROLLER + 0x01150030)
#define CLK_OUT_ENB_PVA1_CPU_SET_0	(CLK_RST_CONTROLLER + 0x01160030)
#define CLK_OUT_ENB_PVA0_APB_SET_0	(CLK_RST_CONTROLLER + 0x0115003c)
#define CLK_OUT_ENB_PVA1_APB_SET_0	(CLK_RST_CONTROLLER + 0x0116003c)
#define CLK_OUT_ENB_PVA0_DMA0_SET_0	(CLK_RST_CONTROLLER + 0x01150018)
#define CLK_OUT_ENB_PVA1_DMA0_SET_0	(CLK_RST_CONTROLLER + 0x01160018)
#define CLK_OUT_ENB_PVA0_DMA1_SET_0	(CLK_RST_CONTROLLER + 0x01150024)
#define CLK_OUT_ENB_PVA1_DMA1_SET_0	(CLK_RST_CONTROLLER + 0x01160024)

#define PMC_IMPL_CNTRL_0		0x0c360000
#define PVAA_POWER_GATE_CONTROL_0	(PMC_IMPL_CNTRL_0 + 0x460)
#define INTER_PART_DELAY_EN		(1 << 31)
#define START_DONE			(1 << 8)
#define PVAB_POWER_GATE_CONTROL_0	(PMC_IMPL_CNTRL_0 + 0x46c)
#define PVAA_CLAMP_CONTROL_0		(PMC_IMPL_CNTRL_0 + 0x468)
#define PVAB_CLAMP_CONTROL_0		(PMC_IMPL_CNTRL_0 + 0x474)
#define CV_RG_CNTRL_0			(PMC_IMPL_CNTRL_0 + 0x8b4)

#define MC_CLIENT_HOTRESET_CTRL_1_0	0x02c20970
#define PVA1A_FLUSH_ENABLE		(1 << 30)
#define PVA0A_FLUSH_ENABLE		(1 << 29)

#define MC_CLIENT_HOTRESET_CTRL_2_0	0x02c2097c
#define PVA1C_FLUSH_ENABLE		(1 << 8)
#define PVA1B_FLUSH_ENABLE		(1 << 7)
#define PVA0C_FLUSH_ENABLE		(1 << 6)
#define PVA0B_FLUSH_ENABLE		(1 << 5)

#define DELAY_100MS	100

#endif
